Shopping Cart Checkout Shipping Cost Download Website

Home

MP3 Player

8051 Tools

All Projects

PJRC Store

Site Map

You are here: OSU8 Microprocessor Schematic OSU8 Core Status Bits Register

Search PJRC

OSU8 Microprocessor Overview CPU Programming Hardware Info Schematic Xilinx Implementation Address Decoder OSU8 Core Normal Size Large Size 8-Bit Data ALU 16-Bit Addr ALU Control State Machine State Register Bus Control Accumulator B Register Status Bits Register 2:1 Mux 8:1 Mux 2:1 Mux Operand Register Program Counter Stack Pointer P1 Pointer P2 Pointer 16-Bit Equals Temp Register 8-Bit Zero Buffers Full Hierarchy Index Implementation Download Files

Status Bits

OSU8 also specifies four output port bits, which may be loaded from the Carry bit. Those port bit latches and the circuitry to load them from the Carry bit are located in the lower right section of this schematic. OSU8's two input port pins are just inputs the multiplexor that loads the carry bit. Thost two input bits are not latched, they just just copied into the carry bit at the instant that a MOV IN0, C or MOV IN1, C instruction is executed.

Return to OSU8 Main Schematic

Complete List of All OSU8 Schematics