OSU8 Microprocessor

PJRC.COM Offline Archive, February 07, 2004
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OSU8 Microprocessor

Overview
CPU Programming
Hardware Info
Schematic

Xilinx Implementation
Address Decoder
OSU8 Core

Normal Size
Large Size
8-Bit Data ALU
16-Bit Addr ALU
Control State Machine
State Register
Bus Control
Accumulator
B Register
Status Bits
Operand Register
Program Counter
Stack Pointer
P1 Pointer

Register
2:1 Mux

P2 Pointer
16-Bit Equals
Temp Register
8-Bit Zero
Buffers

Full Hierarchy Index

Implementation
Download Files

P1 Pointer Register

This is the 16-bit register that holds OSU8's P1 Pointer register. Either of two sources can load the register, depending on the state of SLEB, each of the four nibbles separately enabled by ENLB, ENLT, ENHB, and ENHT. The four separate nibble-wide load signals are required to support the 4-bit immediate load instructions, which can load the P1 register.

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/reg16c_p1.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>

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