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You are here: OSU8 Microprocessor Schematic OSU8 Core Bus Control

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OSU8 Microprocessor Overview CPU Programming Hardware Info Schematic Xilinx Implementation Address Decoder OSU8 Core Normal Size Large Size 8-Bit Data ALU 16-Bit Addr ALU Control State Machine State Register Bus Control Accumulator B Register Status Bits Operand Register Program Counter Stack Pointer P1 Pointer P2 Pointer 16-Bit Equals Temp Register 8-Bit Zero Buffers Full Hierarchy Index Implementation Download Files

Bus Controller

The control section asserts either RD_REQ or WR_REQ, and causes the desired address to appear on bus 16C. For a read request, OSU8's core expects valid data to be present on the Din bus at the next rising edge of the internal clock. For a write request, the data on the Dout bus must have been properly stored before the next rising edge of the internal clock. This simple state machine has 4 external clock cycles to accomplish those tasks.

This simple circuit falls far short of optimizing OSU8's speed, because it breaks the bus cycle into four timing periods, of equal length, during which time only one internal machine cycle is executed. A better bus controller could be designed, to improve OSU8's performance. At the very least, it could use "half cycles" to allow more of the time for the external memory's access time, which probably allow a faster clock.

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