OSU8 Microprocessor

PJRC.COM Offline Archive, February 07, 2004
Visit this page on the live site

Shopping Cart Checkout Shipping Cost Download Website

Home MP3 Player 8051 Tools All Projects PJRC Store Site Map

You are here: OSU8 Microprocessor Schematic OSU8 Core Status Bits 8:1 Mux Search PJRC

OSU8 Microprocessor

Overview
CPU Programming
Hardware Info
Schematic

Xilinx Implementation
Address Decoder
OSU8 Core

Normal Size
Large Size
8-Bit Data ALU
16-Bit Addr ALU
Control State Machine
State Register
Bus Control
Accumulator
B Register
Status Bits

Register
2:1 Mux
8:1 Mux
2:1 Mux

Operand Register
Program Counter
Stack Pointer
P1 Pointer
P2 Pointer
16-Bit Equals
Temp Register
8-Bit Zero
Buffers

Full Hierarchy Index

Implementation
Download Files

8-input MUX

This 8 input mulitplexer is used to select one of many possible bits to loaded into the Carry bit. These sources include the other status bits, the two input port pins, a complemented copy of the carry, and fixed high and low.

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/my_mux8_psw.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>

Return to Status Bits

Complete List of All OSU8 Schematics