OSU8 Microprocessor

PJRC.COM Offline Archive, February 07, 2004
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You are here: OSU8 Microprocessor Schematic OSU8 Core 8-Bit Data ALU 8-Bit 3:1 Mux Search PJRC

OSU8 Microprocessor

Overview
CPU Programming
Hardware Info
Schematic

Xilinx Implementation
Address Decoder
OSU8 Core

Normal Size
Large Size
8-Bit Data ALU

ALU-8 Main
8-Bit Adder
8-Bit Shifter
8-Bit 3:1 Mux
Function Dec
N & Z Bits
8-Bit AND
8-Bit OR
Zero A
Zero B
Compare A
Compare B
Misc Logic

16-Bit Addr ALU
Control State Machine
State Register
Bus Control
Accumulator
B Register
Status Bits
Operand Register
Program Counter
Stack Pointer
P1 Pointer
P2 Pointer
16-Bit Equals
Temp Register
8-Bit Zero
Buffers

Full Hierarchy Index

Implementation
Download Files

8-bit 3-input MUX

This simple group of MUX's passes one of three 8-bit data signals, which come from the gates that compute A AND B, A OR B, and B optionally zeroed and/or inteverted. One of these three operations is always passed into the ALU's adder.

Schematic Drawing

OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/mux3x8.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>

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