PJRC.COM Offline Archive, February 07, 2004
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You are here: OSU8 Microprocessor Schematic OSU8 Core 8-Bit Data ALU Zero B Search PJRC

OSU8 Microprocessor
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B Zero AND Gates

This array of AND gates is used to force the B input to zero, when the BZERO signal is asserted.

Schematic Drawing


OSU8: Simple 8-Bit Microprocessor Design; Paul Stoffregen
http://www.pjrc.com/tech/osu8/sch/and2x8x1_b.html
Last updated: November 28, 2003
Status: These pages are a work-in-progress
Comments, Suggestions: <paul@pjrc.com>
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