Assigned: 7 April 1999
Due: 14 April 1999 at 3:30 PM

Late homeworks will not be accepted.

1. Problem 8.5 from the text.
2. You are given a system with 4 KB pages and 32-bit virtual addresses, and you are designing the virtual memory portion of the OS for this system. You are considering two different schemes, a single-level page table scheme and a two-level page table scheme with 2K entries in the top level page table. The average process on this system has 2.5 MB of code, 5.3 MB of data, and a 768 KB stack arranged in virtual memory as follows:

   0

   232-1

   Code (2.5MB)

   Data (5.3MB)

   empty

   Stack (768KB)

   1. Show how the two level page table scheme translates a virtual address to a physical address. Include the sizes of various bit fields as necessary.
   2. For an average process, how much space is required for page tables using each proposed scheme?
3. For the memory system in problem 2, we are using a TLB to reduce the cost of paging. Suppose the TLB has a hit rate of 99.8%, and incurs no overhead if a translation is found in the TLB. Memory accesses take 50ns, and instructions require 5ns each (excluding memory overhead). How much slower does paging make the computer if:
   1. There is no TLB?
   2. There is a TLB filled in hardware (no additional overhead beyond the memory accesses required)?
   3. There is a TLB filled by software, requiring 10 instructions to fill? Assume that the TLB code doesn't itself cause TLB faults; the code does, however, need to access memory to get at the page tables.
4. Why is it easier to share reentrant code (code that can be executed by more than one process simultaneously) using segmentation as opposed to pure sharing?
5. Problem 9.11 from the text.
6. Problem 9.13 from the text.
7. Problem 9.17 from the text.