UMBC
CMSC 391 -- Programming Microcontrollers
8051 Microcontroller Hardware
The
8051
architecture consists of these specific features:
Eight-bit CPU with:
Register A (the Accumulator)
Register B
Instruction set
Sixteen-bit program counter (PC) and data pointer (DPTR)
Eight-bit program status (PSW)
Eight-bit stack pointer (SP)
Internal ROM or EPROM (8751) of 0(8031) to 4K (8051)
Internal RAM of 128 bytes:
Four register banks, each containing eight registers
Sixteen bits, which may be addressed at the bit level:
128 addressable bits
Eighty bytes of general-purpose data memory
Thirty-two input/output pins arranged as four 8-bit ports: P0-P3
Two 16-bit timer/counters: T0 and T1
Full duplex serial data receiver/transmitter: SBUF
Control registers:
TCON
TMOD
SCON
PCON
IP
IE
©2004, Gary L. Burt