8 bit parallel in shift register





This register accepts a parallel input at the


eight inputs 1-8 and serially shifts in a low to


bit one and shifts out the current value of bit


eight at each consecutive clock pulse. The


following parallel input produces the corresponding


output for the next eight clock pulses followed


by Q = 0 until the next sequence is loaded





Pin | level             Clk | Q


----|-------            ----|---


 1  |   0                1  | 0


 2  |   0                2  | 1


 3  |   1       --\      3  | 0


 4  |   1       --/      4  | 1


 5  |   1                5  | 1


 6  |   0                6  | 1


 7  |   1                7  | 0


 8  |   0                8  | 0











To parallel load this shift register, hold the LD


input low. Clocking is accomplished on the low-


to high level edge of the clock pulse. A direct


reset input overrides all other inputs, including


the clock, and sets all flip flops to zero. 





You can drag this component to another position


by clicking inside the body of the device, hold


the mouse button, move the device to the new


position, and release the mouse button.





