UMBC CMSC 211

UMBC | CSEE

Interrupt Processing on the 80X86

There are 256 interrupts possible on the X86 computers. Any one of which can be caused to executing the instruction:
INTn;cause interrupt n
 Interrupts can be enables or disable with the instructions:
sti ;set I flag to 1, enable
cli ;set I flag to 0, disable
 Memory locations 0 - 1023 hold a four-byte address (segment:offset) in a interrupt vector table for each interrupt handler.

The interruption mechanism is:

  1. When an device wishes to cause an interrupt, it makes an interrupt request that includes the number of the interrupt. When arriving in the CPU it is held until the completion of the current instruction.
  2. At the end of each instruction, before the next instruction is fetched, the CPU checks to see if there are any interrupts waiting. If there is, one is selected for interrupt service and the others are held.
  3. The CPU does the following items:
    1. Push the flag register onto the stack
    2. Disable interrupts.
    3. Push the cs and IP registers.
    4. Load the address of the handler.
The rest is up to the specific interrupt handler, however, they should quickly reenable interrupts (which implies that the handler itself can be interrupted). Any other register will be used must first be pushed onto the stack. The handler then does what it is suppose to do. Finally, the handler must pop the saved registers, and issue a special return:
iret ;return from interrupt.
 This will pop the IP, cs and flag registers, which will also reenable the interrupts.

The interrupt vector table is setup by the boot-up procedure in the BIOS when the computer starts up, setting addresses puter starts up, setting addresses of interrupt handlers for interrupts that the BIOS handles, and initializing the rest to a handler that consists of nothing but the iret instruction. This makes it easy to upgrade the handlers in future releases of the operating system or even to have a different operating system altogether. When the operating system loads, it puts in the address of its handlers where necessary. Additionally, the user can piggy-back on an interrupt, as we shall see.

WARNING: Since interrupts occur at any time, they wipe out anything that had been put onto the stack previously. Never assume that something you popped is still on the stack waiting for you!

UMBC | CSEE |