Lab 4: Verilog and DeMorgans Theorm

Updated Fall 2021 Robucci

Table of Contents

• Lab 4: Verilog and DeMorgans Theorm
  • Table of Contents
  • Objective and Overview
  • Discussion and Theory
    • De Morgan’s Laws
      • A brief overview
      • example
    • Verilog
      • Structural Code Using Verilog Primitives
      • By using provided IC Models (IC74LS08) and (IC74LS32)
      • Tetbench Code for the test
      • Simulating the circuit by iverilog
      • Waveform viewer
    • Icarus Verilog in Windows
      • Method 1: GL servers via MobaXterm
    • Downloading GTKWave onto Lab Windows Computers
  • Prelab
  • Lab Exercise
  • Lab Report Submission

Objective and Overview

In this lab you will learn how to write a structural Verilog for a circuit and simluate it to test its functionality. You will use DeMorgan’s Theorem to manipulate a logical expression to change its mapping to gates. You will use Verilog to describe the circuit. We will learn how a testbench is used to a test the circuit.

Discussion and Theory

De Morgan’s Laws

A brief overview

example

In the following circuit, we are going to convert equation to map to nor gates and a inverter:

(pin numbers in this diagram correspond to pin numbers on your discrete 74LS ICs)

The output of the circuit can be expressed as:
$F = (A + B)\cdot C$
Then we make complement both side of the equation:
$\overline{F} = \overline{(A + B)\cdot C}$
Now we apply the De Morgan rule on the right side of equation:
$\overline{F} = \overline{(A + B)} + \overline{C}$
Finally, we need another complement to get the $F$ from $\overline{F}$
$\overline{\overline{F}} = \overline{\overline{(A + B)} + \overline{C}} \leftrightarrow \overline{\overline{(A + B)} + \overline{C}}$
As the equation shows, the function can be mapped by two nor gates as demonstrated in the following picture. The bubbles represent inversion:

The truth table of this circuit including inputs, output, and intermediate signals are given below:

Inputs			Intermediate Signals in Circuit 1	Intermediate Signals in Circuit 2		Output
A	B	C	p	m	n	F
L	L	L	L	H	H	L
L	L	H	L	H	L	L
L	H	L	H	L	H	L
L	H	H	H	L	L	H
H	L	L	H	L	H	L
H	L	H	H	L	L	H
H	H	L	H	L	H	L
H	H	H	H	L	L	H

Verilog

In the discussion session you are going to use Verilog to simulate the following circuit.

Structural Code Using Verilog Primitives

module first_verilog_str(A, B, C, F);
  input A;
  input B;
  input C;
  output F;

  logic x;
  logic y;

  and(x, C, A);
  and(y, C, B);
  or(F, x, y);

endmodule

As an educational exercise in this lab, you will be provided models of the 74LS series chips with functions pin orders. You can use these to perform a digital simulation with a netlist matching your breadboard circuit.

The IC models are provided here: cmpe212_ic.v

By using provided IC Models (IC74LS08) and (IC74LS32)

module first_verilog_IC(A, B, C, F);
  input A;
  input B;
  input C;
  output F;

  logic x;
  logic y;

  IC74LS08 myand(.Y2(x),.B2(A),.A2(C),.GND(1'b0),.A4(C),.B4(B),.Y4(y),.VCC(1'b1));
  IC74LS32 myor(.Y1(F),.A1(x),.B1(y),.GND(1'b0),.VCC(1'b1));

endmodule

Tetbench Code for the test

To test the functionality of HDL codes unlike High Level Languages(HLL) such as C/C++, Python needs another code. This code is generally called testbench code. In the following testbench, we show how to model the switch in the picture with three reg variable A, B, and C. In this example, we just instantiate the first_verilog_IC module to test the functionality of it.

module test_bench();
   /*anything that you set in the initial begin...end block should be declared as reg.  Here A, B, C stand as the switch operation.*/
   logic A, B, C;      
   /* the outputs of instantiated module in the testbench are defined as wire*/
   logic F;


   /* Instantiate Circuit Here */
    first_verilog_IC uut(.A(A), .B(B), .C(C), .F(F));

   
   /* Testbench Logic */

   initial begin
      $monitor("(%t): A:%b B:%b C:%b F:%b",$time, A, B, C, F);
      /* here each 1000 unit timescale the value of A, B, C are chenged. It seems that we change the switches position*/       
      A = 0; B = 0; C = 0;
      #1000;      
      A = 0; B = 0; C = 1;
      #1000;   
      A = 0; B = 1; C = 0;
      #1000; 
      A = 0; B = 1; C = 1;
      #1000;
      A = 1; B = 0; C = 0;
      #1000;
      A = 1; B = 0; C = 1;
      #1000;
      A = 1; B = 1; C = 0;
      #1000;
      A = 1; B = 1; C = 1;
      #1000;                                     
   end
      
endmodule // test_bench

Simulating the circuit by iverilog

To compile this test bench and make an output with the name of my_out, we would use the following:

iverilog -g2012 -o my_out cmpe212_ic.v first_verilog_IC.v test_bench.v

To run the output:

./my_out

After simulation you should see the result the same as the picture:

By default, the delays embedded in the IC modules are not simulated. To turn them on use the specify flag (the default is no-specify):

iverilog -g2012 -g specify -o my_out cmpe212_lab4.v first_verilog_IC.v test_bench.v

To run the output:

./my_out

The result is:

Waveform viewer

To use a waveform viewer, you must dump the waveforms to a waveform file.
Add the following code to the beginning of the initial begin…end block in your test bench code, on the line just after the begin

$dumpfile("my_out.vcd");
$dumpvars;

Make sure to compile, but then instead you might need use vvp to run the executable in order to produce the waverform dump.

iverilog -g specify -o my_out cmpe212_lab5.v first_verilog_IC.v test_bench.v
vvp ./my_out

To run the waveform viewer, include the file name or simple use the GUI File menu to select the file.

gtkwave my_out.vcd

---

Icarus Verilog in Windows

Method 1: GL servers via MobaXterm

1. download MobaXterm from the below link and install:
   https://mobaxterm.mobatek.net/download-home-edition.html

2. Open MobaXterm then click on Session and select SSH. Write ‘gl.umbc.edu’ in the remote host. Write your umbc user name then run and give your umbc password.
   

3. Discover which shell you are using using the following command

   ps -p $$
   

   • If using bash, you should see something like the following:

         PID TTY          TIME CMD
      536902 pts/12   00:00:00 bash
     

   • If using tcsh (a varient of csh C-Shell) you should see something like the following:

         PID TTY          TIME CMD
     3886339 pts/43   00:00:00 tcsh
     

4. Edit script to setup shell environment

   • For tcsh: Open the .cshrc file in your favorite editor. Example: nano ~/.cshrc

   • For bash: Open the .bashrc file in your favorite editor. Example: nano ~/.bashrc

     alias scripts

     Typically bash aliases are placed in a separate file lke ~/.bash_aliases, but this tutorial was not based on the assume that your account is set up to call this file. If you know better, place your aliases in the .bash_alias file

5. Add the aliases to your startup script

   • tcsh: Go to the bottom and find the last line with an “endif”. Below this line, add the following line- (We are using Dr. Ryan Robucci’s installation)

     echo "Setting iverilog and gtkwave aliases for CMPE212 .cshrc"
     alias iverilog=/afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/iverilog
     alias vvp=/afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/vvp
     

   • bash: add the following to the end of the file

     echo "Setting iverilog and gtkwave aliases for CMPE212 from .bashrc"
     alias iverilog /afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/iverilog
     alias vvp /afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/vvp
     

6. Save the file and exit (you can use Ctrl+s and then Crtl+x)

7. Log out and log back in and verify that the script edits were successful
   You should see a message like this:

   Setting iverilog and gtkwave aliases for CMPE212 ...
   

8. Verify that Verilog is installed

   • Use the following command:

     which iverilog
     

     If installed correctly, the path to the program will be shown

     • bash: /afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/iverilog
     • tcsh: iverilog: aliased to /afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/iverilog

   • Typing the alias commend will show both aliases

     • bash:

       alias iverilog='/afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/iverilog'
       alias vvp='/afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/vvp'
       

     • tcsh:

       alias iverilog /afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/iverilog
       alias vvp /afs/umbc.edu/users/r/o/robucci/pub/iverilog/bin/vvp
       

   • Finally display the syntax help

     iverilog -help
     

     Usage: iverilog [-EiSuvV] [-B base] [-c cmdfile|-f cmdfile]
                     [-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012] [-g<feature>]
                     [-D macro[=defn]] [-I includedir]
                     [-M [mode=]depfile] [-m module]
                     [-N file] [-o filename] [-p flag=value]
                     [-s topmodule] [-t target] [-T min|typ|max]
                     [-W class] [-y dir] [-Y suf] [-l file] source_file(s)
     
     See the man page for details.
     

Downloading GTKWave onto Lab Windows Computers

1. Download gtkwave-3.3.100-bin-win32 from the below link extract the zip file to any location:
   https://sourceforge.net/projects/gtkwave/files/

2. Go to the bin folder of the gtkwave and then run the gtkwave.exe.
   Now you can see the main window of the program the same as the picture:
   

3. To see the waveform of a simulated design:

   • first file->Open New Tab
   • add the *.vcd file which you can have it by simulating design by iverilog(you can learn how to generate this file in the discussion session) On the lab computers, your Linux directory can be found under drive T: (make sure that you logged into AFS)
   • After opening the *.vcd file you have your design in the gtkwave window:
     
   • Click on each module that you want to see the waveform of its signal, and then you can see the list of the signals. Double click on the each signal that you want to see its wave.
   • Now you have the signals in the wave window of the software. Set zoom in and zoom out setting of the window. Finally you can see the waveform.
     

Prelab

For the following circuit, create an alternative implementation using DeMorgan’s Laws, in the same manor as the example. Fill the blanks area and finally depict the NAND-only version implemented of the circuit and complete the Truth Table for both implementations.

1. Function :	$F = C \cdot A + C \cdot B$

2. Complement both side:	$\overline{F}$ =

3. Apply De Morgan rule:	$\overline{F} =$

4. Final NAND-only gate :	$F =$

Finally, draw the schematic form of the NAND-only gate of the circuit:

Last, fill in the following truth table for both implementations.

Inputs					Output			Output
A	B	C	x	y	F	u	v	F

Lab Exercise

Use Verilog to describe both circuits. Create a testbench to demonstrate functionality.
Test the circuit with and without delays. View the results in the waveform viewer.
Capture/save the waveform display as well as the simulation console outputs.

Lab Report Submission

• Submit the schematic and truth tables for both the circuits.
• Submit plots from the waveform viewer for both circuits with and without delay. Report delays in a table in your lab report for both circuits.
• All the plots should be captioned. Mark axes with proper signal names.
• Include code that you prepared for the lab in an appendix section. Comment and properly format the code that you include in the lab report.
• Report in this lab is 10% of the lab grade