Combinational Functions and Circuits

There are a number of functions and circuits that are usually used to build larger circuits. These reusable circuits become functional blocks.

Block Diagram of a Sequential Circuit

Functions of One Variable

X		F = 0	F = X	F = X'	F = 1
0		0	0	1	1
1		0	1	0	1

F = 1

F = X

F = X'

F = 0

Functions of Two Variables

A	B	Y
0	0	I₀
0	1	I₁
1	0	I₂
1	1	I₃

Enabling

We talked about a tri-state buffer where we had a Hi-Z output. Basically, enabling allows an input signal to become an output signal.

Coders And Decoders

When using digital computers to represent data, we put it into binary. We can have it a a 2ⁿ input bits, and 2^m output bits.Putting the data into the code is done by the coder and extracting the data is done by the decorder.

2-to-4 Line Decoder

source: Logic and Computer Design Fundamentals, 3rd Ed., Mano and Kime, 2004, Pearson Prentice Hall

We can use two bits to put a signal on the proper output line when there are four output lines.

Truth Table

EN	A₁	A₀	D₀	D₁	D₂	D₃
0	X	X	0	0	0	0
1	0	0	1	0	0	0
1	0	1	0	1	0	0
1	1	0	0	0	1	0
1	1	1	0	0	0	1

VHDL For A 2-to-4 Decoder

-- 2-to-4 Line Decoder with Enable:  Structural VHDL Description
library ieee, lcdf_vhdl;
use ieee.std_logic_1164.all, lcdf_vhdl.funcprims.all
entity decoder_2_to_4_w_enable is
  port (EN, A0, A1: in std_logic;
        D0, D1, D2, D3 : OUT std_logic;
end 	decoder_2_to_4_w_enable;	

architecture structural_1 of decoder_2_to_4_w_enable is
  component NOT1
      port (in1: in std_logic;
	    out1: out std_logic);
  end component;
  
  component AND2
      port (in1, in2: in std_logic;
            out1: out std_logic);
  end component;

  signal A0_n, A1_n, N0, N1, N2, N3: std_logic;
  begin
    g0: NOT1 port map (in1 => A0, out1 => A0_n);
    g1: NOT1 port map (in1 => A1, out1 => A1_n);
    g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0);
    g3: AND2 port map (in1 => A0, in2 => A1, out1 => N1);
    g4: AND2 port map (in1 => A0_n, in2 => A1, out1 => N2);
    g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3);
    g6: AND2 port map (in1 => EN, in2 => N0, out1 => D0);
    g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1);
    g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2);
    g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);
end structural_1

Verilog For A 2-to-4 Line Decoder

// 2-50-4 Line Decoder with Enable: Structural Verilog Desc.
module decoder_2_to_4_st_v(EN, A0, A1, D0, D1, D2, D3);
  input EN, A0, A1;
  outut D0, D1, D2, D3;
  
  wire A0_n, A1_n, N0, N1, N2, N3;
  
  not
    g0(A0_n, A0),
    g1(A1_n, A1);
  and
    g3(N0, A0_n, A1_n),
    g4(N1, A0, A1_n),
    g5(N2, A0_n, A1),
    g6(N3, A0, A1),
    g7(D0, N0, EN),
    g8(D1, N1, EN),
    g9(D2, N2, EN),
    g10(D3, N3, EN);
endmodule