Homework #3

CMSC 611, Spring 2000

Assigned: 29 Feb 2000
Due: 7 Mar 2000 at 5:45 PM

1. Do problem 3.1 in the text for the following code sequence, assuming that R4 = R3 - 196 at the start of the loop. In addition, write the C code that this assembly language code implements.

   loop:
   LW   R1, 0(R4)
   SLLI R1, R1, #3
   LW   R2, 4(R4)
   ADD  R1, R2, R1
   SW   R1, 0(R4)
   ADDI R4, R4, #4
   SUB  R6, R3, R4
   BNZ  R6, loop

2. Problem 3.3 in the text.
3. Problem 3.10 in the text.
4. You are trying to choose between a history file and a futures file for handling exceptions and restoring values to registers. What information do you need to make your choice? In particular, how could you quantify the cost of using each option? Which option is likely to require more hardware (registers and/or control)? Why?
5. Your measurements have shown that exceptions occur on average once every 500 instructions. The overall CPI of your architecture without exceptions is 1.2, and the CPU runs at 500 MHz. You are considering two approaches to handling exceptions. The first method allows the five stage pipeline to drain completely, cancelling all in-progress instructions currently in the pipeline. The exception instruction then starts in an empty pipeline. The second method uses advanced techniques to keep the pipeline full, but this reduces the processor speed to 475 MHz to accommodate the more complex logic. Assume the CPU has the standard 5-stage DLX pipeline, and that 60% of exceptions are IF faults (page faults, illegal memory access, etc.), 25% are MEM page faults, 5% are illegal instructions (handled in ID), and 10% are ALU faults. Which exception handling method results in a faster CPU? Hint: figure out how many instructions are "wasted" for each type of exception....
6. In a very high-speed processor, it might be necessary to split the ALU stage into two cycles (i.e., the ALU takes two cycles to generate a result). How would this change affect the standard DLX pipeline?
   1. What additional data hazards would be introduced? Assume all possible forwarding paths are implemented.
   2. How could you estimate the performance penalty due to these hazards? Can you place a bound on the maximum penalty to the CPI from making this change?
7. Is there any benefit to having a pipeline in which the clock runs twice as fast but the pipeline is twice as deep (in other words, a pipeline in which each stage is split into two stages that are half as long)? What drawbacks would such an arrangement have?